1. Field of Invention
The present invention relates in general to digital signal processing and in particular, to variable duty cycle clock generation circuits and methods and systems using the same.
2. Background of Invention
In digital signal processing (DSP) architectures, processing operations are typically triggered on either an active rising edge or an active falling edge of a clock or similar timing signal. In some DSP architectures, the execution of the majority of the processing operations is restricted to the active clock phase of the clock period between the each active edge and the following inactive edge. Fewer operations are then performed during the inactive clock phase between the inactive edge and the next active edge. In these DSP architectures, an asymmetric duty cycle clock with an extended active clock phase and a decreased inactive clock phase can improve timing margins and increase overall system speed. For example, in an architecture in which operations are triggered on active falling clock edges, the active low clock phase between each active falling clock edge and the next inactive rising edge is extended, for instance to fifty-five percent (%55) of the total clock period. Consequently, the following inactive high phase between the inactive rising clock edge and the next active clock edge is shortened by an equal amount, in this example to forty-five percent (%45) of the total clock period. In other words, the asymmetric duty cycle for the clock signal, in this example, is %55 to %45 in favor of the active low clock phase.
In other DSP architectures, maintaining a symmetric clock (i.e. having a %50 to %50 high phase to low phase duty cycle) is critical. However, maintaining a precise symmetric clock signal can be a difficult task, especially if the clock signal is generated directly from an external crystal with a nonzero output signal duty cycle error tolerance. Guardbands can be designed into the circuit timing margins to account for clock signal duty cycle variations caused by tolerances in the external crystal, but implementing guardbands sacrifices circuit speed and chip area. Alternatively, symmetric clock signals can be generated using a phase-locked loop (PLL) driven by a voltage controlled oscillator (VCO) running at twice the required frequency. The VCO output is then divided by two (2) to generate the desired base clock frequency. However, this PLL technique also sacrifices the accuracy of the ultimate clock signal duty cycle and adds circuitry to the design, particularly when high speed clocks are being generated.
In sum, new circuits and methods are required for generating accurate timing signals, such as high speed clocks. These circuits and methods should allow for the generation of precise active edges in either symmetric and asymmetric timing signals. Furthermore, the duty cycle of these timing signals should be variable under user control, as required to optimize circuit and system performance.